Compositions and methods for polishing (e.g., planarizing) the surface of a substrate are well known in the art. Polishing compositions (also known as polishing slurries, CMP slurries, and CMP compositions) typically contain an abrasive material in an aqueous solution and are applied to a surface by contacting the surface with a polishing pad saturated with the polishing composition. Typical abrasive materials include metal oxide particles, such as silicon dioxide, cerium oxide, aluminum oxide, zirconium oxide, and tin oxide. U.S. Pat. No. 5,527,423, for example, describes a method for chemically-mechanically polishing (CMP) a metal layer by contacting the surface with a polishing composition comprising high purity fine metal oxide particles in an aqueous medium. The polishing composition is typically used in conjunction with a polishing pad (e.g., polishing cloth or disk). Suitable polishing pads are described in U.S. Pat. Nos. 6,062,968, 6,117,000, and 6,126,532, which disclose the use of sintered polyurethane polishing pads having an open-celled porous network, and U.S. Pat. No. 5,489,233, which discloses the use of solid polishing pads having a surface texture or pattern.
A semiconductor wafer typically includes a substrate, such as silicon or gallium arsenide, on which a plurality of transistors have been formed. Transistors are chemically and physically connected to the substrate by patterning regions in the substrate and layers on the substrate. The transistors and layers are separated by interlevel dielectrics (ILDs), comprised primarily of some form of silicon oxide (SiO2). The transistors are interconnected through the use of well-known multilevel interconnects. Typical multilevel interconnects are comprised of stacked thin-films consisting of one or more of the following materials: titanium (Ti), titanium nitride (TiN), tantalum (Ta), aluminum-copper (Al—Cu), aluminum-silicon (Al—Si), copper (Cu), tungsten (W), doped polysilicon (poly-Si), and various combinations thereof. In addition, transistors or groups of transistors are isolated from one another, often through the use of trenches filled with an insulating material such as silicon dioxide, silicon nitride, and/or polysilicon.
Chemical-mechanical polishing is used to planarize the surface of the metal layers or thin-films during the various stages of device fabrication. Many of the known CMP compositions are suitable for limited purposes. However, the conventional CMP compositions tend to exhibit unacceptable polishing rates and selectivity levels with respect to insulator materials used in wafer manufacture. In addition, many CMP compositions tend to exhibit poor film removal traits for the underlying films or produce deleterious film-corrosion, which leads to poor manufacturing yields.
As the technology for integrated circuit devices advances, traditional materials are being used in new and different ways to achieve the level of performance needed for advanced integrated circuits. In particular, silicon nitride and silicon oxide are being used in various combinations to achieve new and ever more complex device configurations. In general, the structural complexity and performance characteristics vary across different applications. There is an ongoing need for methods and compositions that allow for the removal rates of various layers (e.g., silicon nitride, silicon oxide) to be adjusted or tuned during CMP to meet the polishing requirements for particular devices. The present invention provides such improved polishing methods and compositions. These and other advantages of the invention, as well as additional inventive features, will be apparent from the description of the invention provided herein.